Design and Analysis of 16-bit RISC Processor
Shraddha M. Bhagat, Sheetal Umesh Bhandari · 2018
RISC (Reduced Instruction Set Computer) is a design methodology which supports small and simple set of instructions that all requires the same amount of time to execute. A design of 16-bit RISC processor is presented in this paper, using the Verilog HDL. The RISC processor comprises of the blocks mainly ALU, Controller, Register files, and Data memory unit. The proposed processor carried out with the help of von Neumann architecture, having only one shared memory for instruction and data. The proposed RISC processor which can be very, simple and clean to investigate contains 15 instructions. Modelsim is used for logical verification. The proposed RISC processor is analyzed using Xilinx ISE tool.