A 135-mW 1.70TOPS Sparse Video Sequence Inference SoC for Action Classification
Thomas Chen, Ching‐En Lee, Chester Liu, Zhengya Zhang · IEEE Journal of Solid-State Circuits · 2019
An inference system-on-chip (SoC) is designed to extract spatio-temporal features from videos for action classification. The SoC contains an inference core that implements a recurrent neural network in three processing layers. High sparsity is enforced in each layer of processing, reducing the complexity by two orders of magnitude and allowing multiply accumulates to be replaced by select accumulates. Spatio-temporal kernel and activation compression are applied to reduce memory by 43% and 64%, respectively. The design is demonstrated in a 2.53-mm240-nm CMOS chip with an OpenRISC core, providing control and classification. With the inference core extracting spatio-temporal features and a soft-max classifier programmed on the OpenRISC core, the SoC classifies KTH Human Action Data Set at a 76.7% accuracy. At 0.9 V and 250 MHz, the SoC achieves 1.70TOPS, dissipating 135 mW.