Asynchronous MOUSETRAP Implementation of AES-128 Encryption Using 65nm Standard Cells
Chris Vincent Densing · 2018
Asynchronous pipelines offer advantages of flexibility and modularity over synchronous pipelines. In this work, the AES-128 encryption algorithm was implemented using the MOUSETRAP asynchronous pipelining technique. MOUSETRAP allows easy integration with existing standard-cell based design methodologies. Combinational logic blocks were implemented using automatic synthesis tools, while sequential elements of the pipeline were designed by hand. This work was able to achieve a maximum throughput of 312.5 million operations/sec, a latency of 14.374 ns, and average power of 91.38 mW at maximum throughput using 65-nm standard-cell CMOS technology.