Switching Activity Analysis of Shifters and Multipliers for Application to ROM-less DDFS Architecture Selection for Low Power Performance
Chua‐Chin Wang, Hsiang-Yu Shih · 2018
A dynamic power estimation method for critical logic cirucits used in ROM-less direct digital frequency synthesizer (DDFS) designs is proposed, including the analysis of switching activity of adders, shifters, and multipliers. Most important of all, the analytic solutions of the logic circuits' bit switching activity are dervied, respectively. As soon as the partitions of the [(π)/2] and the polynomial interpolation equations are given, the proposed method is able to assess the overall switching activities such that the power profile of different combination of partitions and equations can be predicted before any physical implementation using logic circuits. The accuracy of the power dissipation profile with respect to the estimation using the state of art is increased by 10 ~ 78 %.