HSTL IO Standard Based Energy Efficient FIR Filter Design on 28nm FPGA
Shivani Madhok, Navdeep Singh, Jasleen Kaur, Khyati Nanda, Sweety Dabas, Minal Dhankar · International Journal of Control and Automation · 2015
In this research paper, we have designed an energy efficient FIR Filter that is very much useful in digital signal processing (DSP).FIR is a finite impulse response (FIR) filter is a filter whose impulse response is of finite duration.In this paper we have aimed to design a FIR Filter that consists of three inputs and one output.The three inputs are input data that is 8 bit or 1 byte (finite), clock and reset.The output is 18 bits (finite) wide.The code has been implemented in Xilinx ISE Design Suite 14.2 and results were tested on 28nm FPGA platform.The design has been tested on Kintex-7.Power analysis has been done at different operating frequencies.In this paper we have done frequency scaling technique to obtain energy efficient design.The temperature has been kept constant that is 25 degree Celsius.Airflow and heat sink are main parameters while analyzing the thermal dissipation in the circuit [12].In this work we have taken constant value of air flow and heat sink.Airflow has been kept 250 LFM and medium Heat sink.In this paper we have taken HSTL (High Speed Transceiver Logic) IOSTANDARD.HSTL family consists of HSTL _I, HSTL_II, HSTL_I_18 and HSTL_II_18, HSTL_I_12 and the analysis has been done on these IO standards.We can conclude that there can be 23-33% saving of total power dissipation by using frequency scaling technique.