Low Power Implementation of Advanced Encryption Standard using Efficient Shift Registers in 45 nm Technology
Yogendra Singh Sikarwar, N. S. Murty · 2018
Security is the most important aspects of Internet of Things (IoT). The popularity of IoT increased the need of Radio Frequency Identification (RFID) chips and smart cards that are energy efficient and more secure against attacks. Lightweight encryption circuit is essential for any IoT application, which is required to be energy and area efficient. This paper introduces an AES implementation using energy efficient shift register with ADOC and RTPG gating technique which improves the efficiency of the AES implemented design. Comparison is done with the current AES implemented designs with respect to power, area and delay. The proposed AES design shows 29.32 percent improvement in power consumption over register renaming based AES design.