6.3 A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET
Matteo Pisati, Fernando De Bernardinis, Paolo De Pascale, Claudio Nani, Marco Sosio, Enrico Pozzati, Nicola Ghittori, Federico Magni, Marco Garampazzi, Giacomino Bollati, Antonio Milani, Alberto Minuti, Fabio Giunco, Paola Uggetti, Ivan Fabiano, Nicola Codega, Alessandro Bosi, Nicola Carta, Demetrio Pellicone, Giorgio Spelgatti · 2019
The enormous availability of data on the internet and the increased computational power available in the cloud require a constant increase in the bandwidth needed to transport data across the network. In order to mitigate the cost of infrastructure, the industry has proposed standards for 56Gb/s PAM-4 interfaces that can support legacy channels in conjunction with forward error correction (FEC) techniques. The reduced signal to noise ratio (SNR) available with PAM-4 modulation vs. NRZ requires sophisticated signal processing, making DSP-based solutions very attractive in terms of performance but, so far, at the expense of extra power vs. classical analog solutions. This paper demonstrates that this trade-off can be broken and presents a compact ADC/DAC DSP-based long-reach transceiver in 7nm FinFET technology that operates seamlessly from 3.5-to60Gb/s in PAM-4 (from 1-to-30Gb/s in NRZ mode) and consumes less than 250mW at 56Gb/s. The presented IP extends the deployment of DSP-based transceivers from repeater/re-timer applications to big ASICs with a very large number of ports.