VHDL Implementation Of 64-bit ALU
IOSR Journal of Electronics and Communication Engineering · 2013
In this paper VHDL implementation of 64-bit arithmetic logic unit (ALU) is presented.The design was implemented using VHDL Xilinx Synthesis tool ISE 9.1 and targeted for Spartan device.ALU was designed to perform arithmetic operation and logical operations such as addition , subtraction using 64-bit fast adder, logical operations such as AND, OR, XOR and NOT operations, 1'scomplement, rotate operations and compare.ALU consist of two input registers to hold the data during operation, one output register to hold the result of operation, 64-bit fast adder with 2's complement circuit to perform subtraction and logic gates to perform logical operation.The maximum propagation delay is 13.588ns and power dissipation is 38mW.