Network Load Analysis During Test Mode for the Network-on-Chip Reused Test Access Mechanisms
Muhammad Adil Ansari · 2018
On-chip interconnects have been reused for transporting test data to and from different modules of a chip. Similarly, several schemes have been presented to reuse network-on-chip (NoC) as test access mechanism (TAM). There is different load on the on-chip network by different test schemes those result in different energy consumption. Such test schemes are classified in this work, based on the number of input/output access points (IO-APs), number of time slots, and network protocol compliance/defiance. Moreover, the network load is analyzed for different test schemes in term of flit injection rate. The analysis showed that a development in NoC fabric better utilizes the network resources during test operation and reduces network load.