Construction of a Low Multiplicative Complexity GF (24) Inversion Circuit for Compact AES S-Box
Jia Jun Tay, M. L. Dennis Wong, Ming Ming Wong, Cishen Zhang, Ismat Hijazin · 2018
In this work, we construct a compact composite AES S-Box by deriving a new low multiplicative complexity GF (24) inversion circuit. A deterministic tree search algorithm is applied to search for constructions that are optimum in terms of multiplicative complexity. From the results, the circuit with the smallest gate count is selected for GF (24) inversion. To the best of our knowledge, the proposed AES S-Box requires the smallest gate count to date with the size of 112 gates and depth of 25 gates.