VLSI-Architecture of Radix-2/4/8 SISO Decoder for Turbo Decoding at Multiple Data-rates
Rahul Shrestha, Ashutosh Sharma · 2018
We propose flexible-architecture for soft-input soft-output (SISO) decoder with radix-2/4/8 modes to support multiple data-rates. This work presents designs of major internal blocks of SISO decoder using extensive steering logic to support multiple radix operating-modes. These architectures enable efficient clock-gating of our decoder for low-power consumption in different operating modes. Subsequently, we have aggregated eight SISO decoders with quadratic-permutation-polynomial (QPP) interleavers/de-interleavers to design parallel-turbo decoder architecture which can operate in multi-radix mode. Suggested SISO decoder is ASIC synthesized and post-layout simulated in UMC 65 nm-CMOS process. Performance analyses in AWGN channel environment showed that the bit-error-rate (BER) of 10-4could be achieved at 5 dB and 0.8 dB for SISO and turbo decoders respectively. Implementation result shows that the suggested SISO decoder could achieve throughput in the range 270-810 Mbps with the corresponding power consumption range of 12.24-37.67 mW. In comparison to the state-of-the-art, our design achieved 38% higher throughput and 61% lower power consumption. Similarly, our multi-radix parallel-turbo decoder is hardware prototyped in 28 nm-CMOS Zynq-FPGA board. It delivers a range of data-rates from 80-320 Mbps operating at 160 MHz of clock frequency for 8 iterations.