A Multiple Clock Domain Design of High-radix Montgomery Multiplication for Simplicity
Naoki Fujieda, Yusuke Ayuzawa, Masato Hongo, Shûichi Ichikawa · 2018
This paper presents a case for intra-module multiple clock domain design in FPGAs using a high-radix Montgomery multiplier. Our design aims at simple hardware description from algorithm description, avoiding the decrease of clock rate by a long combinatorial path. According to our evaluation with 1024-bit modular exponentiation units, the calculation time reduced by 1.0% on average. The additional logic units for the proposed design was 2,556 LUTs and 1,043 flip-flops per multiplier at a maximum.