ENERGY EFFICIENTWEIGHTED TEST PATTERN GENERATOR BASED BIST ARCHITECTURE
G. S. Sankari, M. Maheswari · 2018 2nd International Conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC)I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC), 2018 2nd International Conference on · 2018
The recent technology aims at complex systems ,multiple computational algorithms,High efficient hardware which works with low power.But to operate all these systems the power requirement for testing is huge.To solve this problem in testing a Built in Self Testing methodology is used.Along with this BIST concept Weighted Pseudo random pattern Generator is used to minimize the power consumption and dissipation.The input patterns will increase the switching activity which in turn increase the energy requirement. Hence, to reduce the switching activity the weighted patterns are generated. This reduces number of patterns given to the CUT and hence the switching activity factor also reduced.The proposed weighted pattern generated architecture was designed and implemented in Altera Cyclone FPGA. Implementation results show that the proposed BIST architecture consumes less power.