An Efficient Hardware Design of Demodulating Fingers for CDMA Mobile System
Sang Yun Hwang, Jae‐Seok Kim · 1999
This paper presents an efficient hardware architecture of demodulating fingers to demodulate the multi-path propagating signals in CDMA Mobile System. We design a new architecture of demodulating fingers which share the single arithmetic unit to reduce the hardware complexity. This arithmetic unit performs MAC(Multiplication and Accumulation) operations of all demodulating fingers. We design the proposed architecture using VHDL and implement it on Altera FPGA chip. The proposed architecture is suitable for IS-95 based CDMA PCS system. It contains about 23K logic gates when the number of demodulating finger is 3. The hardware complexity of our proposed architecture is decreased by 11% to be compared with the conventional one. Three demodulating fingers for MC-CDMA which demodulate 7 channels contain about 42K logic gates. Our proposed system is shown to be very useful for hardware architecture which uses multiple demodulating fingers, and also for Multi-code CDMA system in which several channels are demodulated simultaneously.