FPGA Implementation of optimized Reversible Linear Feedback Shift Registers
K. Rajesh, Galiveeti Umamaheswara Reddy · 2018 2nd International Conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC)I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC), 2018 2nd International Conference on · 2018
One of the most potential technologies for low-power VLSI is reversible computing and it has enormous applications has found in low-power CMOS, Quantum computing, Nanotechnology, QCA. The main condition of reversibility is every individual input and outputs are connected internally. In this paper, we proposed optimized reversible design of linear feedback shift registers (LFSR) while designing the LFSR, we have designed optimized Serial input serial output (SISO), Serial input parallel output(SIPO) up to N-bit with reversible gates and it has explored in terms of delay, quantum cost, garbage outputs. Complete simulation and the synthesis process are carried out with the Xilinx ISE 14.7 and are dumped on FPGA Spartan-6E.