Fault-Tolerant Network-on-Chip Design for Mesh-of-Tree Topology Using Particle Swarm Optimization
P. Veda Bhanu, Pranav Venkatesh Kulkarni, Sarthak Jain, J. Soumya, Linga Reddy Cenkeramaddi, Henning Idsøe · 2018
As the size of the chip is scaling down the density of Intellectual Property (IP) cores integrated on a chip has been increased rapidly. The communication between these IP cores on a chip is highly challenging. To overcome this issue, Network-on-Chip (NoC) has been proposed to provide an efficient and a scalable communication architecture. In the deep sub-micron level NoCs are prone to faults which can occur in any component of NoC. To build a reliable and robust systems, it is necessary to apply efficient fault-tolerant techniques. In this paper, we present a flexible spare core placement in Mesh-of-Tree (MoT) topology using Particle Swarm Optimization (PSO) by considering IP core failures in NoC. We have experimented by considering several application benchmarks reported in the literature. Comparisons have been carried out, (i) by varying the percentage of faults in the MoT network with fixed network size and (ii) by considering the each core has been failed in the given application benchmark. The results show limited overhead in communication cost while providing fault-tolerance.