Design of a Quadruple Decimal Logarithmic Converter
Md. Moshiul Islam, Md. Liakot Ali · 2018
This paper presents the design of a high precision Quadruple (128-bit) decimal logarithmic converter. It has been designed using IEEE industry standard Verilog HDL and simulated using ModelSim software. It is the first of its kind that uses a 128-bit floating-point arithmetic for high precision. Desired functionality and accuracy of the converter have been tested using different test data. The converter is low power and low logic gate counts since digit-by-digit iterative technique that does not require look-up tables, curve fitting, decimal-binary conversion, or division operations has been used. Finally the accuracy of the converter has been tested with that of CASIO calculator which shows that the result is correct up to 34-digit. It has also been compared with that of other researchers which shows its superior performance in terms of precision.