Path-Balanced Logic Design to Realize Block Ciphers Resistant to Power and Timing Attacks
Partha De, Chittaranjan Mandal, Udaya Parampalli · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2019
In this paper, binary decision diagram (BDD)-based dual-rail precharge logic circuit schemes have been developed to counter differential power analysis attacks, timing attacks, and early propagation attacks. Different precharge logic schemes (top precharging, top-bottom precharging, bottom precharging, and symmetric nMOS bottom precharging) are presented and evaluated. The hallmark of our circuit schemes is that an identical number of switchings is ensured on each circuit path. The transistors are interconnected to create pull-up and pull-down paths to outputs by way of binary decisions based on the input variables, so as to realize the required Boolean function. A simple synthesis algorithm for mapping a given Boolean function to such a BDD-based circuit is also presented. Experimentation has been carried out on two 4-, 16-, 32-, and 64-bits S-boxes to establish resistance of our circuits to power analysis attack and to highlight the low-power characteristics with the help of attributes such as peak power variance, average power, propagation delay, normalized standard deviation of power, and normalized energy deviation. Differential power attacks such as difference of mean and correlation power analysis have been carried out. Resilience to the early propagation effect is also demonstrated.