Flat FPGA Fabrics Derived from 2D-Benes-BFT-Pyramid Networks with Optimizations and Enhancements
Venkat Konda · 2019
Hierarchical FPGA fabrics based on 2D-BFT-Pyramid networks with transformations and optimizations even though offer significant area, power and performance savings still have several drawbacks compared to 2D-Mesh based FPGA fabrics. For example, hierarchical multi-stage fabrics are replicated at tile level of certain tile size do not offer consistent results regardless of the placement of the benchmarks emulated and certain precious routing resources are usable only if the signal traverses that particular hierarchy. We present several enhancements, techniques, and optimizations to transform hierarchical multi-stage networks into flat multi-stage networks i.e., make them replicable for each logic block in both multiplexers and wires. We also propose techniques to provide cascadable wires of arbitrary length with single multiplexer delay to traverse several wires of signal path or same stage connections, to enable multiple signal U-turns as opposed to only one U-turn inherent in a multi-stage network. We achieved the goal of making multi-stage network based FPGA fabric to seamlessly replace any existing 2D-Mesh based fabric, yet keeping everything else intact including placement, routing and all CAD Tools. We implemented the flat multi-stage networks based FPGA fabrics in a few commercial FPGAs with ~3X area savings and significant improvements in other dimensions and also the routing runtime in parity. We conclude with illustration of the benefits and absolutely no drawbacks for multi-stage network based Flat FPGA fabrics compared to prevailing 2D-Mesh network based fabrics. The foregoing Flat FPGA Fabric technology was patent protected since September 7, 2011 in US9374322, US9509634 and their continuation patents.