Fully-parallel 25 MHz 2.5 Mb CAM
Kenneth I. Schultz, F. Shafai, Richard L. Gibson, A. Blusckhe, D.E. Somppi · 2002
In a fully-parallel CAM, all stored bits are compared to the search data in one clock cycle. In traditional implementations, the result of a word search is determined by a dynamic NOR of bit comparison results. This leads to two match line transitions per mismatched word per search and excessive power dissipation, since no more than one match is expected. If the dynamic NOR is replaced by a dynamic NAND, transitions occur only on matches, and power savings are realized.