Method of RTL Debugging When Using HLS for HW Design : Different Simulation Result of Verilog & VHDL
Sang Un Park, Tae Pyeong Kim, Mee Zee Lee, Yong Beom Cho · 2018
HLS (High-Level Synthesis) is useful hardware design technologies using High level language (C, C++ and System C) higher than RTL (Register Transfer Level). But there is error case in which the different simulation result of Verilog & VHDL when verifying in the RTL simulation step using HLS. In this paper, We propose the causes of these problems and how to resolve them. Furthermore, we suggest how to solve similar problems with ASIC design using HLS.