2-D Failure Bitmap Compression Using Line Fault Marking Method
Keewon Cho, Youngwoo Lee, Sungyoul Seo, Sungho Kang · 2018
As memory densities have rapidly increased, memory testing and repairing processes are the major keys to prevent the decline in the yield. For redundancy analysis (RA), fail addresses should be extracted by the external automatic test equipment (ATE) and stored into the failure bitmap. However, full size of the failure bitmap can be a huge burden on the ATE costs. In order to reduce the storage size, this paper presents a new failure bitmap compression method. The proposed method marks all of the addresses of the line fault, so that repairing solutions can be easily decided. Experimental results show that the proposed compression method greatly reduces the size of failure bitmap while minimizing the failure data loss.