Fast HUB Floating-Point Adder for FPGA
Julio Villalba, Javier Hormigo, Sonia González-Navarro · IEEE Transactions on Circuits & Systems II Express Briefs · 2019
Several previous publications have shown the area and delay reduction when implementing real number computation using half-unit biased (HUB) formats for both floating-point and fixed-point. In this brief, we present an HUB floating-point adder for field-programmable gate array (FPGA) which greatly improves the speed of previous proposed HUB designs for these devices. Our architecture is based on the double path technique which reduces the execution time since each path works in parallel. We also deal with the implementation of unbiased rounding in the proposed adder. Experimental results are presented showing the goodness of the new HUB adder for FPGA.