Efficient Folded SC Polar Line Decoder
Yuxuan Huang, Zaichen Zhang, Xiaohu You, Chuan Zhang · 2018
This paper aims at designing a hardware efficient architecture for successive cancellation (SC) polar decoder. Existing literatures have shown that SC polar decoder can be implemented with O(M) processing elements and O(M) memory elements, where M is the code length. In this paper, a folding scheme based on line architecture of successive cancellation is proposed to achieve such hardware complexity. Given 2m-bit code and 2n nodes, we can conveniently achieve an efficient decoder implementation with the proposed design approach. Also a tractable mapping relationship between node activation and clock index is proposed. To validate the efficiency of the proposed approach, line architecture SC decoder with m = 3 and n = 1 and line architecture SC decoder with m = 3 and n = 2 is implemented with Altera Stratix V FPGA.