Hardening FPGA-based AES implementations against side channel attacks based on power analysis
M.A.W. Thoonen · 2019
Differential Power Analysis (DPA), is a type of Side Channel Attack (SCA) which exploits the power-consumption-dependent information leaks to extract the secret key of an AES implementation on an ASIC or FPGA. In this project, we would like to investigate how the power profile of an FPGA-based AES implementation could be modified in a manner that hinders DPA. Specifically, it will be explored whether changing the timing / the structure / the Look-Up Table (LUT) contents of the circuit will prevent this security breach. This will be done using RapidSmith2, a toolset which allows LUT-level manipulations of a netlist, for an implementation on Xilinx FPGAs. Apart from checking whether the information in the power profile of an FPGA is obscured, it also has to be ensured that the functionality of the AES implementation is preserved. The AES circuit will be implemented on a Zedboard Xilinx FPGA evaluation and prototyping board.