VLSI architecture for list successive-cancellation decoding of polar codes
Mahsa Mousavi · 2017
List successive cancellation decoder (LSCD) architectures have been recently proposed for the decoding of polar codes to achieve high decoding performance. However the existing architectures for updating the partial sums of all the list candidate paths scale with the code length and hence induce significant area and delay overhead for polar codes with long code length or list size. In this thesis, a list high performance partial-sum network (LHPPSN) is proposed based on a folded partial-sum network (PSN) architecture of which the complexity does not scale with the code length. A design based on replicating units of high performance PSN and lazy copying is presented, first. Then, to improve the area and performance, some new methods using indices copying and management are proposed. In addition, by exploiting the properties of the PSN, the complexity is further reduced by sharing the path copying logic of the PSN. Experimental results show that the proposed LHPPSN improves the area and delay significantly especially for long code and long list size, when compared to the state-of-the-art LSCD architectures.