Variation Enhancement of Arbiter PUFs with Asymmetric Layout
Yunxi Guo, Timothy Dee, Akhilesh Tyagi · 2018
Arbiter PUF (APUF) is a popular style of physical unclonable function (PUF) that has been used in many security applications. The amount of process variation of an APUF is an important parameter strongly influencing its resolution. Although various attempts have been made to increase APUFs' random variation from the circuit design prospective, little work has been done to enhance manufacturing mismatch through transistor-level layout. In this work, we propose a novel layout strategy for enlarging inner-die delay variation of an APUF circuit in an area neutral manner. The mechanism separates a pair of racing delay units by an appropriate distance. Corresponding variation enhancement is quantified according to Pelgrom's mismatch model. Cadence Monte Carlo sampling shows the proposed scheme improves delay variation of 0. 13um technology 128-stage APUFs with minimum transistor size by as much as 8% without significantly affecting the inter-die hamming distance.