New methods for the compaction testing of multiple-output digital circuits
Micaela Serra · 1987
A new approach, called compaction, is proposed for the testing of multiple-output circuits. Testing is applied in parallel to all outputs and produces a single signature, that is an attribute or set of attributes which change in the presence of a fault. Space compaction testing is directly applicable to built-in self-test. We prove that criteria exist for detecting whether or not a line is testable, using a deterministic approach without the need for extensive simulation. Further, the fault model is extended to include bridging faults, rather than being limited solely to single stuck-at faults. General conditions are presented which specify deterministically when a fault is testable by a spectral sum signature. Such a signature is composed of a weighted sum of one or more spectral coefficients, which simply reflect a form of counting compaction applied to all outputs. The syndrome count is a special case. From the evaluation of the conditions, guidelines for design for testability are inferred. Of great significance is the application of the theory to highly structured multiple-output networks like programmable logic arrays (PLA's). These occur frequently in current VLSI designs, and they can be deeply embedded within circuits, so that they are hard to test. For these examples space compaction testing gives full coverage for all single stuck-at faults, bridging faults, and cross-point faults.