FPGA Implementation of Multiplierless Low-Pass FIR Differentiator
Václav Sova, Martin Brablc, R. Grepl · International Conference on Mechatronics - Mechatronika · 2018
In this paper we present, that if we appropriately choose the parameters of the maximally flat FIR differentiator, the coefficients of the filter will have a common divisor which is reciprocal to a power of two. That means that the entire filter can be implemented in a very cost-effective way using only shift and add operations, which is beneficial mainly when the filter is implemented on the FPGA. Proposed differentiator was implemented on an FPGA and tested in real time. At the end of the article we compare the FPGA resource utilization for the proposed maximally-flat FIR differentiator and a differentiator designed using a common approach.