Probabilistic Analysis of Power-Gating in Network-on-Chip Routers
Nasim Nasirian, Reza Soosahabi, Magdy Bayoumi · IEEE Transactions on Circuits & Systems II Express Briefs · 2018
By increasing the number of cores on a chip in the past decade, the network-on-chip technology has been developed to address scalability issues that arise in highly demanded multi-core architectures. Nevertheless, interconnection networks impose additional hardware overhead such as: routers, network interfaces, and increased power consumption. Power-gating (PG) the idle components has been employed in some recent research as a promising solution to decrease the static power consumption while its drawbacks such as wake-up delay and power overhead should be addressed properly. In this brief, a probabilistic analysis has been conducted to estimate the PG efficiency in queuing-theory context and a control unit has been proposed to manage the sleep signal assertion to buffer entries based on the analysis results. Our simulation results show an average improvement of static power saving of about 40% compared to naive PG, and 20% with respect to related works where it can enhance the average latency by about 20% without significant impact on overall throughput.