From multicore LDPC decoder implementations to FPGA decoder architectures: a case study
Yann Delomier, Bertrand Le Gal, Jérémie Crenne, Christophe Jégo · 2018
Last generation high-level synthesis (HLS) tools enables hardware generation of software descriptions speeding up hardware development times. LDPC codes are involved in many digital standards even 5G, generating high quality architecture from software description is needed for Software Defined Radio (SDR) or Cloud-RAN (C-RAN) systems. Previous works in the field focused on reusing many-core software description of LDPC decoding algorithm for hardware generation purpose. In this article we demonstrate that multicore oriented ones once transformed for HLS are more suitable for hardware decoder generation. Indeed, throughputs and hardware complexities observed are closer to handmade LDPC decoders in comparison with related works. Presented results open new perspective for fast integration or prototyping of ECC architectures.