Mitigation of Soft and Hard Errors in FPGA-Based Pacemakers
Gehad I. Alkady, Ihab Adly, Hassanein Hamed Amer, Tarek K. Refaat · 2018
Nowadays, there is a great improvement in Implantable Medical Devices (IMD) manufacturing. The Pacemaker is one of the commonly used IMDs responsible for curing improper heart rate pacing. As a real-time critical device, it requires a powerful flexible platform such as FPGAs. Moreover, it should have an area-optimized architecture. In this research, a novel architecture of the pacemaker is proposed through the integration of some modules of the pacemaker together: The Analog to Digital converter (A2D) and the pulse generator modules. Both are implemented inside the same FPGA as a single chip solution. This reduces the footprint of the pacemaker without having any negative impacts on system performance. The system is implemented using the Xilinx Vivado tool. FPGA-based pacemakers are prone to both SEUs and permanent faults. Consequently, a suitable Fault-Tolerant technique should be applied to increase system reliability. Two schemes are investigated in this research: Two Duplication With comparison (2DWC) and Sift-Out. Both use Dynamic Partial Reconfiguration (DPR) for fault recovery. Markov Models for both techniques are constructed to evaluate system reliability. A case study shows that the Sift-Out architecture is the optimum technique for the system.