IJTAG Integrity Checking with Chained Hashing
Senwen Kan, Jennifer Dworak · 2018
The JTAG port is a well-known vector for attacks that attempt to gain access to a chip's internal circuitry. Such attacks may modify or extract proprietary data and can lead to misconfigured chips and IP theft. This paper uses a hash-based signature created through the history of the data shifted into and out of a device via IJTAG to provide a measure of continuous authentication and guard against malicious modification of data sent to/from the device under test. The proposed approach also provides evidence of tampering through the JTAG port as unauthorized access attempts will change the recorded signature.