Variable Latency Division
Peter-Michael Seidel · 2018
We propose a variable-latency implementation of iterative, subtractive division, where the partial remainder is encoded in carry-save representation. Digit selection is implemented based on the redundant partial remainder representation using a combination of leading-zero prediction, binary shifting and a small number of comparators. The implementation targets low-power operation, but for higher performance it could be adopted to higher radices.