Fast Design of Reliable, Flexible and High-Speed AWGN architectures with High Level Synthesis
Yann Delomier, Bertr Le Gal, Jérémie Crenne, Christophe Jégo · 2018
In this paper, rapid prototyping of reliable, flexible and high-speed AWGN hardware architectures are presented. To do so, different methods to generate high precision Gaussian noise are discussed. These methods are compared on an algorithmic level and then implemented from a High Level Synthesis (HLS) tool. Unlike previous works that have focused on area-efficient but time-consuming hand-made architectures, HLS tools enable fast and reliable design of architectures. This work proposes reliable architectures in terms of Gaussian noise quality for a minimum of design effort. Designed architectures are compliant with the IEEE-754 standard for floating-point arithmetic. The architectures are implemented onto field-programmable gate array (FPGA) Virtex-7 device. Comparing to hand-made architectures, the synthesized architectures are similar in terms of performance with a reasonable hardware resources overcost.