A 65-nm CMOS 3.2-to-86 Mb/s 2.58 pJ/bit Highly Digital True-Random-Number Generator With Integrated De-Correlation and Bias Correction
Venkata Rajesh Pamula, Xun Sun, Sung Kim, Fahim ur Rahman, Baosen Zhang, Visvesh Sathe · IEEE Solid-State Circuits Letters · 2018
This letter presents a highly digital, technology scalable, and energy-efficient cryptographic-quality true random number generator (TRNG). The proposed architecture presents a balanced approach to TRNG design, relying on a simpler, noncryptographic quality physical random number generator (phyRNG) combined with energy-efficient integrated post-processing to de-correlate and de-bias thephyRNG bitstream. Operating at a supply voltage (${V}_{\text {dd}})$of 0.53 V, a 65-nm CMOS prototype of the TRNG achieves a peak energy-efficiency of 2.58 pJ/bit. TRNG bitstreams pass all NIST randomness benchmarks over a${V}_{\text {dd}}$range of 0.5–1.05 V across −20 °C–100 °C, demonstrating its efficacy and robust operation over a wide${V}_{\text {dd}}$and temperature range.