Power-Efficient and Memory-Aware Approximate Hardware Design for HEVC FME Interpolator
Wagner Penny, Mariana Ucker, Italo Machado, Luciano Volcan Agostini, Daniel Palomino, Marcelo Porto, Bruno Zatt · 2018
Challenges related to mobile video coding systems are of utmost importance for researchers, especially regarding issues posed by the limited battery capacity and computational resources. The current state-of-the-art video coding standard is the High Efficiency Video Coding (HEVC), which implements computationally intensive coding tools, such as the Fractional Motion Estimation (FME). As a way to deal with real-time constraints, hardware acceleration is necessary. Furthermore, the usage of hardware accelerators allied to approximate computing is also an alternative to improve performance and save power/energy. In this work, we present a power-efficient and memory-aware approximate configurable hardware design for the HEVC FME interpolator. The proposed design is capable of realtime interpolation of UHD 4K and 8K (Ultra High Definition - 2160p@60fps and 4320@60fps) videos when synthesized using a 45nm standard-cell library, with a power dissipation ranging from 9.78mW to 50.4mW.