DPPM Reduction Methods and New Defect Oriented Test Methods Applied to Advanced FinFET Technologies
W.D. Howell, Friedrich Hapke, Edward Brazil, S. Venkataraman, Ramyanshu Datta, Andreas Glowatz, W. Redemund, J. Schmerberg, Anja Fast, Janusz Rajski · 2018
This paper presents DPPM reduction results achieved with new Defect Oriented Test (DOT) methods/patterns applied to designs manufactured in advanced FinFET technologies. Focus of this paper is on Timing-Aware Cell-Aware Test (TA-CAT) patterns targeting small-delay defects of FinFET transistors, and a new DOT method which explicitly targets chip layout dependent cell-neighborhood defects. Test results from traditional Stuck-at/Transition patterns, from traditional CAT patterns, from TA-CAT patterns, and as well from cell-neighborhood patterns, applied to FinFET technology designs, will be presented in this paper. In addition, a correlation to System-Level-Test fails will be discussed.