Reduced Complexity Processor for Teaching Computer Architecture
Hamid S. Timorabadi · Proceedings of the Canadian Engineering Education Association (CEEA) · 2018
This paper proposes the application of a Reduced Complexity Processor (RCP) as a tool in teaching computer architecture. The design and implementation of the RCP as well as its effectiveness is reported. The proposed RCP is a single-cycle, 8-bit processor. The processor currently used in the course is a soft-processor, Nios-II, by Altera. Nios-II is a complex, single-cycle, 32-bit processor that cannot easily be dissected for students’ realization of computer archi-tecture. Teaching RCP alongside Nios-II allows to eliminate some of the unnecessary complexities that prevent students from achieving a rather better realiza-tion of computer system functionality. The intention is also to actively involve students in design process by providing a platform that allows students to modify and build their own processor