Design of Neural Network Architecture using Systolic Array Implemented in Verilog Code
Trio Adiono, Grasia Meliolla, Erwin Setiawan, Suksmandhira Harimurti · 2018
In this paper, an implementation of a neural network model using systolic arrays, programmed in Verilog Code, is presented. The neural network model is mapped in a three-layer perceptron in forward mode. Dependency graph is also provided to illustrate the operations in each phases of the neural network model. Afterwards, the operations in a linear directional of systolic array is realized using a recursive iterative algorithm. The modelling in Verilog code is later confirmed with the MATLAB code for 9-input-output structure. The result proofs that the neural network architecture based on systolic array is successfully implemented in Verilog code.