FPGA Implementation of 32 Bit Complex Floating Point Multiplier Using Vedic Real Multipliers with Minimum Path Delay
K. Deergha Rao, Prakasam Muralikrishna, Ch. Gangadhar · 2018 5th IEEE Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON) · 2018
Floating point Complex numbers multiplication is an essential operation in DSP and communication applications with high speed and less power requirement. Hence, this paper presents an IEEE 754 format 32 × 32 bit complex floating point multiplier using four floating point real multipliers solution with minimum path delay. Each 32 bit real floating multiplier requires a 24 bit fixed point real multiplier for mantissa multiplication. Based on the Indian Vedic mathematics sutra called URDHVA TIRYAKBHYAM, two architectures for 24×24 bit Vedic real multiplier are proposed for mantissa multiplication in 32 bit floating point real multiplier. The two architectures are evaluated to choose one having less path delay for use in the proposed complex floating point multiplier. The four floating point real multipliers solution for the proposed multiplier is coded in VHDL for implementation on Kintex-7 FPGA. Finally, the results of the proposed multiplier are compared with that of the Booth and Array multipliers.