Decimal Multiplication Using Combination of Software and Hardware
Riaz-ul-haque Mian, Michihiro Shintani, Michiko Inoue · 2018
Decimal arithmetic through software is slow for very large scale application, while it needs extra overhead through hardware. A balanced strategy can overcome both the issues. Our proposed methods based on IEEE 754-2008 standard for floating-point arithmetic is a combination of software and hardware. Software with some area efficient decimal component (hardware) is used to design the multiplication. Analysis in different platforms shows that depending upon requirment, the proposed methods can reduce the execution time by 24%-81% compared to a standard software library with 25%-94% less hardware compared to an area efficient full decimal multiplier.