Importance of Multi-parameter SAT Attack Exploration for Integrated Circuit Security
Kyle Juretus, Ioannis Savidis · 2018
An analysis of the effects variable ordering, initial constraints, and the phase heuristic have on the number of iterations required to complete the SAT attack is described. The characterization of variable ordering through the generation of 1,000 random netlist gate orderings results in as much as 276% variation in the number of iterations required to execute the SAT attack. Setting the initial conditions of the SAT solver results in up to a 636% increase in the average number of iterations required to complete the SAT attack for an OR tree circuit topology. Modifying the phase heuristic of the SAT solver is also analyzed, indicating that the AND-tree structure does not always provide enhanced security against a SAT-attack. The described analysis demonstrates that security is dependent on a variety of conditions that are not represented in a single execution or implementation of the SAT attack, requiring further evaluation of circuit security against the SAT attack.