A Low Power Test Pattern Generator for Minimizing Switching Activities and Power Consumption
Jugal Kishore Bhandari, M. Krishna Chaitanya, G. Venkat Rao · 2018 International Conference on Inventive Research in Computing Applications (ICIRCA) · 2018
For all integral self-test circuits linear feedback shift register (LFSR) is employed to come up with the test vectors to be applied. the standard or conventional model of test pattern generator (TPG) could generate some perennial check patterns, and also all possible combinations of test patterns that unnecessarily will increase the test power while not contributive abundant to the fault coverage. Based on TPG style, the chip space additionally will increase, tributary for the overall power consumption of the IC. This paper presents approach known as low power-positioned complements bits test vector generation (LP-PCBTVG) technique with partially fixed bits sequence and bit insertion (either 0 or 1) techniques. Hence, the application of ultimate output vectors of LP-PCBTVG circuit over device/circuit under test decreases the total test power compared with LFSR-based BIST. And also by complementing of few output bits of LP-BCTVG in an exceedingly arranged and nominal order, we will scale back the massiveness of TPG which can contribute in reducing size of IC. The obtained simulation results prove that this method will scale back the test power consumption in conjunction with higher fault coverage in comparison with LFSR-based BIST.