Speed optimization of 32 bit single precision floating point multiplier through pipelining in VHDL
Tajinder Pal Singh · DergiPark (Istanbul University) · 2018
Thepaper is presenting the architectural method for speed optimization of floatingpoint multiplier involves increasing the frequency by implementing pipelines inthe design using VHDL language. The whole algorithm of IEEE 754 standard 32 bitsingle precision floating point multiplier have two pipelining stages, whichimprove the frequency rate of clock to 422.556 MHz and result the output in2.367ns. The design also handles the overflow/ underflow cases withnormalization for the better accuracy of the result. Xilinx vertex 5 FPGA is targeted for the design and the simulationis done on XilinxISE simulator.