Memory-system requirements for convolutional neural networks
Antara Ganguly, Virendra Pal Singh, Rajeev Muralidhar, Masahiro Fujita · Proceedings of the International Symposium on Memory Systems · 2018
Energy efficiency of the underlying memory systems is a huge issue in most neural network accelerator designs. It is imperative to understand the characteristics and behavior of data in the algorithm of neural networks to gain an insight into their impact on memory-systems. The current work studies such impacts of convolutional neural networks on the energy efficiency of memory-systems by analyzing the structuring of datasets in convolutional neural networks, their memory space and bandwidth requirements, the energy efficiency of their accesses in DDR memory systems versus 3D-stacked DRAM systems and the future direction of this area. Also, one possible architectural implementation using the near-data processing capabilities of highly parallel heterogeneous 3D-stacked DRAM chips of Micron's Hybrid Memory Cube is demonstrated which shows an improvement of above 90% in energy efficiency for acceleration of convolutional neural networks.