ASIC Coprocessor for 254-bit Prime-Field Pairing based on General Purpose Arithmetic Unit on Quadratic Extension Field
Hiromitsu Awano, Makoto Ikeda · 2018
A hardware accelerator for the 254-bit prime-field optimal-ate pairing over Barreto-Naehrig (BN) curve is proposed. The data path of the proposed crypto processor is designed to compute five Fp^2operations, a multiplication, three addition/subtractions, and an inversion in parallel. We further propose a design methodology to automate the instruction scheduling by using a combinatorial optimization solver, with which the total cycle count is reduced to 1/2 compared with ever reported. The proposed crypto processor is designed by using a 65 nm siliconon-thin-box (SOTB) CMOS process. The post-layout simulation revealed that the proposed accelerator can compute a pairing in 62.3 μ seconds when a typical operating voltage of 1.2 V is applied, which corresponds to 8.4× improvement from the current stateof-the-art ASIC-based accelerator.