A 655Mbps Successive-Cancellation Decoder for a 1024-bit Polar Code in 180nm CMOS
Hye-Yeon Yoon, Seung-Jun Hwang, Taehwan Kim · 2018
This paper presents the implementation of a high-throughput successive-cancellation decoder for a 1024-bit polar code. The proposed decoder processes the kernels in two successive layers in a fused manner within a cycle, so as to reduce the cycle count taken to decode a codeword. In addition, the log-likelihood ratios are represented in a redundant form to realize a high-speed kernel processing. As a result, the cycle period is not lengthened even with the fused kernel processing and thus achieving a high throughput. Implemented in 180nm CMOS, the proposed decoder shows the throughput of 655 Mbps for the rate-1/2 code. In terms of the throughput efficiency, the proposed decoder is 3.51 times superior to the previous state-of-the art one.