Interface Logic Generation for VHDL-Specified Components
Jeff Collins, Smita Bakshi, Karl D. Nelson · 1998
This paper presents a new approach to automate the generation of interface logic required to interface two components, possibly with incompatible communication protocols. Our tool is specifically targeted to handle synchronous and asynchronous protocols with diverse timing constraints such as propagation, setup and hold times and multiple operation modes such as read, write and burst mode. Since the components and the generated interface logic are specified in VHDL, we expect our tool to seamlessly integrate into a system synthesis environment. So far, we have successfully tested our approach on interfacing processors including the i8051, m68k, and mb86930 with several DRAMs and SRAMs. 1. Introduction Embedded systems are typically implemented with diverse components, including processors, ASICs, memories, and FPGAs. A problem that arises in the synthesis of such heterogeneous systems is to physically interface the various components to one another. One approach to this problem is tak...