Memory-efficient Error Correction Scheme for Flash Memories using GPU
Arul K. Subbiah, Tokunbo Ogunfunmi · 2018
In this paper, we present an alternate method to organize the parity bits of Bose-Chaudhuri-Hocquenghen (BCH) encoder on a Flash memory array. Previous methods for BCH error correction scheme requires parity bytes to be stored within a given block thus reducing the ability to scale up for higher bit error correction capabilities. A new memory organization of the parity bits in the user area is proposed, so the limitation of the number of bit errors to be corrected is removed. Without sacrificing the throughput, this method provides a LUT approach where the parity bits, for a given user data block, are stored in local GPU memory. The experimental results show that, in the case of BCH (8191, 7983, 16), there are no limitations imposed by the spare area for the number of bit errors to be corrected. Also, there is no speed degradation in bit error correction by utilizing the user data area for parity bits with the proposed GPU implementation.